Advances in the field of semiconductor integrated circuits (ICs) have brought about higher levels of integration. Accordingly, semiconductor manufacturing process advancements are driving the corresponding geometric dimensions of semiconductor devices to decreasingly smaller values. 10 micrometer (μm) gate lengths, for example, were common in the 1970's, but continuously advancing semiconductor manufacturing processes have reduced gate lengths to well below 100 nanometers (nm) for deep sub-micron integrated circuit (IC) design.
One key challenge in deep sub-micron design is the increase in process variation, which may lead to significant IC performance fluctuation in key operating parameters such as propagation speed and leakage power. Temperature, aging, and other sources of variation may also contribute to performance fluctuations within the IC. As a result, design specifications for the IC must be much more stringent than would ordinarily be imposed, so as to accommodate for such performance variation.
A conventional method to reduce the effects of performance variation is to detect when the IC's propagation speed differs from the specified propagation speed for the IC. Decreased magnitudes of supply voltage and/or transistor body biasing may be employed, for example, to compensate for propagation speeds above the specified propagation speed. Conversely, increased magnitudes of supply voltage and/or transistor body biasing may be employed to compensate for propagation speeds below the specified propagation speed.
In particular, by reducing/increasing one or both of the supply voltage and/or transistor body bias, a commensurate reduction/increase in the propagation speed may be realized, since a directly proportional relationship exists between supply voltage/transistor body bias and propagation speed. A significant power reduction may also be realized when reduction of the propagation speed is desired, since supply voltage and transistor body bias each exhibit an exponential and directly proportional relationship to leakage power.
Conventional speed characterization of an IC may be performed at wafer sort, or final product test, to determine, for example, whether the IC's actual propagation speed is different from the IC's specified propagation speed. Propagation speed test results may then be stored within non-volatile memory of the IC for subsequent usage by a control circuit when compensation of the IC's propagation speed is desired.
Automated test equipment (ATE), for example, may be used to ascertain the propagation speed that is exhibited by the IC. A communication interface, such as an inter-IC (I2C) communication bus, may then utilize bi-directional, 2-wire communication to store and verify the propagation speed test results within the non-volatile memory of the IC. In a subsequent compensation process, a programmable voltage regulator and/or body biasing circuit may then be utilized to provide the requisite supply voltage and/or transistor body bias, respectively, that is required to adjust the propagation speed to within specification.
Such a characterization and compensation process, however, requires that each IC be characterized, whether or not the propagation speed is out of specification, because the programmable voltage regulator and/or body biasing circuit nevertheless requires the pre-recorded test data in order to set their respective output voltage levels. Furthermore, non-volatile memory and a communication interface are also required to store and verify the pre-recorded test data. Still further, dynamic variations in IC performance levels, such as may be caused by temperature or aging effects, cannot be compensated.
In other conventional control circuits, such as illustrated in FIG. 1, an oscillator, such as voltage controlled oscillator (VCO) 104, may be utilized in conjunction with a dedicated external frequency reference signal, REFERENCE, to detect and compensate for the exhibited propagation speed of the IC. The control circuit of FIG. 1, for example, utilizes feedback to control the magnitude of the power supply voltage, VCC, and/or the transistor body bias voltage, Vbb, so that the frequency provided by oscillator 104 matches the dedicated external frequency reference signal, REFERENCE. By using a dedicated external reference signal whose frequency is substantially equal to the specified propagation speed of the IC, appropriate voltage magnitude levels may then be selected via feedback for the power supply voltage, VCC, and/or the transistor body bias voltage, Vbb, so that the output frequency of oscillator 104 matches the dedicated external frequency reference signal, REFERENCE.
In operation, counter 102 counts the number of rising/falling edge occurrences of the dedicated external frequency reference signal, REFERENCE, and counter 106 counts the number of rising/falling edge occurrences of the signal provided by oscillator 104. Comparator 108 then determines the relative frequency difference between the two signals and generates a control signal that is indicative of the detected frequency difference. Regulator control 110 and bias control 112 then utilize the frequency difference control signal from comparator 108 to program the magnitude of the regulated voltages, VCC and Vbb, as provided by regulators 116 and 114, respectively, in accordance with the frequency difference control signal.
By operation of the feedback to oscillator 104, the frequency difference between the dedicated external frequency reference signal, REFERENCE, and the signal provided by oscillator 104 is substantially removed. Since oscillator 104 is implemented within the IC under test, oscillator 104 exemplifies the propagation speed of the IC under test because oscillator 104 is subject to variations that may affect the propagation speed of oscillator 104. As such, by controlling the frequency of operation of oscillator 104 through feedback of the regulator control and bias control feedback voltages, VCC and Vbb, the propagation speed of the IC under test may be adequately selected.
The control circuit of FIG. 1, however, requires a dedicated frequency reference signal in order to adequately select the propagation speed of the IC under test. If the dedicated frequency reference signal is generated external to the IC under test, then the cost and complexity of the system is adversely affected because a dedicated frequency reference signal must be provided and maintained. If, on the other hand, the dedicated frequency reference signal is generated internal to the IC under test, then the dedicated frequency reference signal is susceptible to the same process, temperature, aging, and other variations that affect the propagation speed of the IC under test.